Topics / Pipelining and async overlap

Performance topic

Pipelining and async overlap

Keep every unit busy: overlap I/O with compute, double buffering, prefetching, and asynchronous copies on GPUs.

1,374proven techniques
42pitfalls: tried, then slower
430repositories
551from papers

Examples from real commits

ROCm/composable_kernel 3.5× Delay V-tile prefetch until after softmax to reduce register live ranges and eliminate spills. proof: commit →

Languages

  • C++353
  • CUDA175
  • Python147
  • Rust99
  • C83
  • Go44

Hardware

  • NVIDIA GPU512
  • CPU260
  • GPU200
  • x8660
  • AMD GPU23

Fields

  • GPU465
  • data & compression282
  • general228
  • graphics132
  • networking104

Where these come from

Repositories with the most techniques on this topic in the database:

triton-lang/triton · 11MaterializeInc/materialize · 10icl-utk-edu/magma · 9vortexgpgpu/vortex · 9kvcache-ai/Mooncake · 9HazyResearch/ThunderKittens · 9lance-format/lance · 8linkedin/Liger-Kernel · 8NVIDIA/cudnn-frontend · 8meta-pytorch/torchrec · 8

Ask Claude for the full answer

Each technique comes with its bottleneck, measured speedup, trade-offs, conditions and the commit or paper behind it, served to Claude through MCP.

claude mcp add --transport http adtomic https://www.adtomic.co/mcp

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Related topics

Bit packing and smaller typesLazy evaluationZero-copyBranchless programmingInlining and devirtualization